I want to make sure I’m answering the right question—are you asking about the number of distinct resistor‐material layers (e.g. TiN, TaN, NiCr, etc.) supported in a FinFET back-end process versus in a gate-all-around nanosheet flow? Or do you mean the number of channel-or-stress-engineering materials used in the transistor body when those devices are operated as very short “resistors”? Any chance you can point me to the specific slide/paper or give a bit more context?

Integrated resistors in both FinFET and gate-all-around (nanosheet) CMOS flows are manufactured in the back-end-of-line (BEOL), using thin-film “resistor stacks” that typically consist of:

1. Resistive film
   – In advanced FinFET HKMG processes, foundry-provided resistor films are most often one of three materials:
     • Titanium-based nitrides (TiN)
     • Tantalum-based nitrides (TaN)
     • Silicon-chromium alloys (SiCr)
   EE Times

2. Barrier/adhesion layer
   – A thin liner (often Ta or TaN) to prevent copper diffusion and to promote adhesion between the resistive film and the surrounding dielectrics.

3. Inter-level dielectric (ILD)
   – Silicon dioxide (SiO₂) or low-k dielectric deposited above and below the resistor film to isolate it from metal routing layers.

4. Metal contacts and interconnects
   – Tungsten (W) or cobalt (Co) “via plugs” to contact the resistor ends, and copper (Cu) wires in the upper metallization levels to route signals.

5. Photoresist
   – A light-sensitive polymer (e.g., chemically amplified resist) applied during photolithography to pattern the resistor geometry to sub-100 nm dimensions. Samsung Newsroom

How they’re put together at the nanoscale

1. Deposition of the resistor stack

   • PVD/CVD is used to blanket-deposit the barrier/adhesion layer and then the resistive film across the entire wafer.

   • An ILD is deposited before and after the resistor layers to electrically isolate them from neighboring structures.

2. Photolithographic patterning

   • A photoresist layer is spin-coated, exposed with deep-UV or EUV light through a mask, and developed to leave behind a high-resolution resist pattern where the resistor should remain.

3. Anisotropic etch

   • The exposed resistive film and barrier layers are etched (typically by reactive-ion etching) down to the underlying ILD, forming the final resistor shape (often a serpentine to maximize length in minimal area).

4. Dielectric fill and planarization

   • The photoresist is stripped, the ILD is blanket-deposited to fill any trenches or gaps, and chemical-mechanical polishing (CMP) planarizes the surface.

5. Via/contact formation and metallization

   • Vias are etched through the ILD, lined with a thin barrier, and filled with W or Co to connect to the resistor ends.

   • Further ILD and metal layers (Cu) are built up to complete the interconnect network.

Because each BEOL “resistor” essentially layers and shapes just a handful of purpose-built films—and relies on the same lithography and etch tools used everywhere else in CMOS—you end up with roughly five distinct material systems (resistive alloy, barrier, dielectric, conductor, plus photoresist) yet achieve feature sizes down into the low tens of nanometers.

Most of the other “widgets” on a modern CMOS chip—transistors, capacitors, diodes, deep-trench isolation, metal-insulator-metal (MIM) capacitors, etc.—are built using exactly the same repertoire of thin-film and patterning sub-processes you see for integrated resistors. In fact, you can boil virtually every layer in a chip down to some combination of:

1. Film deposition (CVD, PVD, ALD, implantation/diffusion)

2. Lithography (spin-on resist, exposure, development)

3. Anisotropic etch (RIE or wet etch)

4. Dielectric fill & planarization (oxide or low-k deposit + CMP)

5. Metallization/via fill (barrier + W or Co plugs, then Cu damascene)

Front-End vs. Middle vs. Back-End

• FEOL (Front-End-of-Line) builds the active devices (wells, isolation, gate stacks, source/drains). A typical FinFET process will use on the order of 20–30 distinct mask layers—each mask layer representing one cycle of deposition → litho → etch (and often followed by a thermal/anneal step) SpringerLink.

• MEOL (Middle-End-of-Line) handles silicidation, spacer formation, and contact preparation—typically a handful of additional masks between FEOL and BEOL.

• BEOL (Back-End-of-Line) builds the wiring. Advanced nodes today routinely stack 9–11 metal layers, and each metal level again follows deposit → litho → etch → CMP → via fill → CMP ScienceDirectcerc.utexas.edu.

Because each metal or film layer requires its own deposition, patterning, and planarization cycle, you end up with several hundred individual process steps across the full front-to-back flow.

Passive Elements (Resistors, Capacitors, MIMs, Inductors)

Every passive element simply “rides” on one of those mask layers:

• MIM capacitors use a metal bottom plate, a thin high-k dielectric, a metal top plate—each blanket-deposited then patterned and etched.

• Deep-trench or STI capacitors etch deep trenches, line them with oxide or nitride, fill with polysilicon—again deposition → litho → etch → fill → CMP.

• On-chip inductors and RF passives are laid out in the top few metal layers, patterned and etched like any other interconnect.

So aside from the specialized materials (high-k dielectrics, metal alloys for resistors, low-k insulators), every component is assembled via the same 4–5 core sub-processes per layer—just on different mask levels depending on whether you’re making a gate, a via, a resistor, or a capacitor.

At its heart, almost every modern “microchip” begins life as a monocrystalline silicon wafer:

1. Monocrystalline silicon substrate

   • Silicon crystals are grown—most commonly by the Czochralski (CZ) method—into large single-crystal boules, then sliced and polished into thin wafers (150–300 mm in diameter) of extremely pure, defect-free silicon serious-science.orgWikipedia.

   • This wafer is the substrate on which all devices (transistors, capacitors, resistors, interconnects) are built “in and upon” the silicon surface Wikipedia.

2. Doping & isolation

   • Selected regions of the silicon are doped (with boron, phosphorus, arsenic, etc.) to form p-type or n-type regions, creating the p-n junctions that underlie transistor action.

   • Isolation structures (e.g. shallow trench isolation, STI) are etched into the silicon and back-filled with oxide to keep devices electrically separate.

3. Gate stacks and device layers

   • Thin films of gate dielectrics (SiO₂ or high-k materials) and gate metals/polysilicon are deposited, patterned (via lithography + etch), and annealed to form the transistor gates.

   • Sidewall spacers, source/drain implants, silicide contacts, etc., are built up in successive FEOL/MEOL steps.

4. Interconnect “back end”

   • Multiple layers of dielectric (SiO₂ or low-k), metal wiring (Cu), vias (W or Co), and barrier layers are deposited, patterned, and planarized to route signals between devices.

Where does etching fit in?

• Etching (both “wet” chemical and “dry” plasma/RIE) is integral to the original chip-making process, not something done afterward.

  • After each lithography step—whether defining transistor gates, isolation trenches, contact holes, or resistor/capacitor patterns—the exposed films are selectively removed by etching to transfer the mask pattern into the underlying material Number AnalyticsSamsung Newsroom.

• You’ll find dozens of etch steps in a full FEOL→BEOL flow, each tuned to remove a specific material (oxide, nitride, silicon, metal alloy, etc.) without attacking neighboring layers.

In other words, chip fabrication isn’t a matter of “etching a finished chip” but of layer upon layer of deposition → lithography → etch (→ anneal/CMP) until the complete integrated circuit emerges on the silicon wafer.